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2015, 22nd IEEE International Conference on High Performance Computing HiPC 2015. Proceedings, Pages 145-154

Hardware-Transactional-Memory Based Speculative Parallel Discrete Event Simulation of Very Fine Grain Models (04b Atto di convegno in volume)

Santini Emanuele, Ianni Mauro, Pellegrini Alessandro, Quaglia Francesco

This article presents an innovative runtime support for speculative parallel processing of discrete event simulation models on multi-core architectures, which exploits Hardware-Transactional-Memory (HTM) facilities for the purpose of state recoverability. In this proposal, the speculative updates on the state of the simulation model are executed as concurrent HTM-based transactions that are also in charge of detecting whether the update is consistent with the advancement of logical-time along model execution. Our proposal is fully transparent to the application code. Hence, our HTM-based run-time support can host conventionally developed discrete event models relying on the concept of event-handlers to be dispatched by an underlying simulation engine. Experimental data show that our proposal provides 75% to 92% of the ideal speedup on an Intel Haswell based platform (equipped with 4 physical cores and HTM support) for discrete event models with event granularity ranging between 2 and 12 microseconds. The data also show that these same models cannot be executed efficiently on top of a last generation parallel discrete event simulation platform employing software-based recoverability
ISBN: 978-146738487-2; 978-1-4673-8489-6; 978-1-4673-8488-9
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